1. Technical Field
The following description relates to a liquid crystal display (LCD), and more particularly, to an array substrate for LCDs.
2. Discussion of the Related Art
In-plane switching (IPS) LCDs, in which a plurality of electrodes are alternately disposed at one of upper and lower substrates and liquid crystal is aligned between the substrates to thereby display an image, are being recently developed as a type of LCD.
Generally, IPS LCDs adjust the light transmittance of liquid crystal having dielectric anisotropy by using an electric field and thus display an image. Here, a color filter substrate with a color filter array formed therein and a thin film transistor (TFT) substrate with a TFT array formed therein are coupled to each other with liquid crystal therebetween, thereby forming an IPS LCD.
The TFT array substrate includes a TFT, a pixel electrode, and a common electrode that are formed in each of a plurality of cell areas that are formed by intersection between a plurality of gate lines and data lines. The TFT switches a data signal, applied from a corresponding data line, to the pixel electrode in response to a gate signal from the gate line. The pixel electrode receives a data signal from the TFT to thereby drive the liquid crystal, and the common electrode receives a common voltage that becomes a reference for swing of data voltages in driving the liquid crystal. The liquid crystal is twisted with an electric field that is generated with the data signal of the pixel electrode and the common voltage of the common electrode, and thus adjusts a light transmittance, thereby realizing a gray scale.
The TFT array substrate for IPS LCDs includes a TFT area, a pixel area, a data line area, a gate pad area, and a data pad area, and may further include a plurality of contact holes for electrically connecting different layers. However, in a related art array substrate for the IPS LCD, the damage of a lower layer and the inter-layer short are caused in electrically connecting the different layers through the contact holes, and particularly, the frequency of occurrence of the drawbacks is high in the gate pad area.
Hereinafter, drawbacks that can occur in the gate pad area of the related art array substrate for LCDs will be described with reference to FIGS. 1 to 6.
FIGS. 1 to 5 are sectional views for describing a related art method of manufacturing a gate pad area of an array substrate for LCDs.
First, as illustrated in FIG. 1, a gate pad 110, a gate insulating layer 120, a first passivation layer 130, and a photo acryl layer 140 are sequentially formed on a substrate 100.
Subsequently, as illustrated in FIGS. 2 and 3, a first metal layer 150 is formed on the photo acryl layer 140, and a second passivation layer 160 is formed on the first metal layer 150.
Subsequently, as illustrated in FIG. 4, a contact hole 180 for exposing the gate pad 110 is formed by patterning the second passivation layer 160, the first passivation layer 130, and the gate insulating layer 120.
Subsequently, as illustrated in FIG. 5, a second metal layer 170 that is connected to the gate pad 110 through the contact hole 180 is formed.
However, in the related art process of manufacturing the gate pad area of the array substrate for LCDs, some drawbacks are caused when a contact hole is deep or a step height between stacked layers is large.
Such drawbacks will be described in detail with reference to FIGS. 6A and 6B.
FIG. 6A is an enlarged sectional view of a portion A of FIG. 5, and FIG. 6B is an enlarged sectional view of a portion B of FIG. 5.
FIG. 6A is a sectional view illustrating the disconnection of the second metal layer 170 in a process that forms the contact hole 180 for exposing the gate pad 110 by patterning the second passivation layer 160, the first passivation layer 130, and the gate insulating layer 120, and then forms the second metal layer 170 connected to the gate pad 110. As illustrated in FIG. 6A, when a step height between the gate pad 110 and the second metal layer 170 is large, the depth of the contact hole 180 becomes greater, and thus, the second metal layer 170 is not conformally formed, causing the disconnection of the second metal layer 170.
FIG. 6B is a sectional view illustrating a defective contact between the gate pad 110 and the second metal layer 170 in a process that forms the contact hole 180 for exposing the gate pad 110 by patterning the second passivation layer 160, the first passivation layer 130, and the gate insulating layer 120, and then forms the second metal layer 170 connected to the gate pad 110. As illustrated in FIG. 6B, in an etching process of forming the contact hole 180, a plurality of etched layers are thick, and thus, when the gate insulating layer 120 that is the lowermost layer to be etched is not completely etched and thus a residual layer is left, a contact between the gate pad 110 and the second metal layer 170 is not made due to the residual layer of the gate insulating layer 120.
The above-described limitations of the related art array substrate for LCDs are as follows.
First, when a step height between the gate pad and the second metal layer is large, the depth of the contact hole that is formed for electrically connecting the gate pad and the second metal layer becomes greater, and thus, the second metal layer cannot conformally be formed on the surface of the contact hole, causing the disconnection of the second metal layer.
Second, in the etching process of forming the contact hole 180, many layers are stacked between the gate pad and the second metal layer or the stacked layers are thick, and thus, when the gate insulating layer 120 that is the lowermost layer to be etched is not completely etched and thus a residual layer is left, a contact between the gate pad 110 and the second metal layer 170 is not made due to the residual layer of the gate insulating layer 120.